Multi-rate, multi-port, gigabit serdes transceiver

ABSTRACT

A multi-port Serdes transceiver includes multiple parallel ports and serial ports, and includes the flexibility to connect any one of the parallel ports to another parallel port or to a serial port, or both. Furthermore, the multi-port transceiver chip can connect any one of serial ports to another serial port or to one of the parallel ports. The substrate layout of the multi-port Serdes transceiver chip is configured so that the parallel ports and the serial ports are on the outer perimeter of the substrate. A logic core is at the center of the substrate, where the logic core operates the serial and parallel data ports, and the bus that connects the data ports. The bus can be described as a “ring” structure (or donut “structure”) around the logic core, and is configured between the logic core and the data ports. The ring structure of the bus provides efficient communication between the logic core and the various data ports.

CROSS-REFERENCED TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. ProvisionalApplication No. 60/421,780, filed on Oct. 29, 2002, which isincorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention generally relates to serial de-serializerintegrated circuits with multiple high speed data ports, and moreparticularly to a serial and de-serializer chip that includes thefunctionality to switch between multiple high speed data ports.

[0004] 2. Background Art

[0005] High speed data links transmit data from one location to anotherover transmission lines. These data links can include serialdeserializer data links (i.e. SERDES) that receive data in a parallelformat and convert the data to a serial format for high speedtransmission. SERDES data links can be part of a backplane in acommunications system (e.g. Tyco Backplane 30-inch trace).

[0006] In a high speed back plane configuration, it is often desirableto switch between multiple Serdes links. In other words, it is oftendesirable to switch between any one of multiple Serdes links to anotherSerdes link, and to do so in a low power configuration on a singleintegrated circuit.

BRIEF SUMMARY OF THE INVENTION

[0007] A multi-port Serdes transceiver includes multiple parallel portsand serial ports, and includes the flexibility to connect any one of theparallel ports to another parallel port or to a serial port, or both.Furthermore, the multiport transceiver chip can connect any one of theserial ports to another serial port or to one of the parallel ports. Themulti-port Serdes transceiver is able to operate at multiple data rates.

[0008] The multi-port Serdes transceiver also includes a packet biterror rate tester (BERT). The packet BERT generates and processes packettest data that can be transmitted over any of the serial ports toperform bit error testing. The packet BERT can monitor (or “snoop”)between the serial ports. In other words, if data is being transmittedfrom one serial port to another serial port, the packet BERT can captureand store a portion of this data for bit error testing.

[0009] The substrate layout of the multi-port Serdes transceiver chip isconfigured so that the parallel ports and the serial ports are on theouter perimeter of the substrate. A logic core is at the center of thesubstrate, where the logic core operates the serial and parallel dataports, and a bus that connects the data ports. The bus can be describedas a “ring” structure (or donut “structure”) around the logic core, andis configured between the logic core and the data ports. The ringstructure of the bus provides efficient communication between the logiccore and the various data ports.

[0010] The Serdes transceiver described herein is highly flexible andcan be configured to provide multiple different transceiver productsfrom enabling and disabling various serial and parallel data ports. Thisis accomplished using a configuration logic circuit thatenables/disables these data ports. As a result, several differenttransceiver products, with different capabilities and price points, canbe configured from a single semiconductor die.

[0011] Further features and advantages of the present invention, as wellas the structure and operation of various embodiments of the presentinvention, are described in detail below with reference to theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The present invention is described with reference to theaccompanying drawings. In the drawings, like reference numbers indicateidentical or functionally similar elements. Additionally, the left-mostdigit(s) of a reference number identifies the drawing in which thereference number first appears.

[0013]FIG. 1 illustrates a multi-port Serdes chip according toembodiments of the present invention.

[0014]FIG. 2 further illustrates the multi-port Serdes chip including aparallel-to-serial conversion according to embodiments of the presentinvention.

[0015]FIG. 3 further illustrates the operation of the transceiver 100 inthe routing of serial data between ports according to embodiments of thepresent invention.

[0016]FIG. 4 illustrates a multi-port Serdes transceiver 400, which isone embodiment of the transceiver 100.

[0017]FIG. 5 illustrates a substrate layout of the multi-port Serdestransceiver chip according to embodiments of the present invention.

[0018]FIG. 6 illustrates a section of the bus 106 according toembodiments of the present invention.

[0019]FIG. 7 further illustrates the bus 106 having equal lengthtransmission lines according to embodiments of the present invention.

[0020]FIG. 8 illustrates a transceiver 800, which one configuration ofthe transceiver 400.

[0021]FIG. 9 illustrates a transceiver 900, which is anotherconfiguration of the transceiver 400.

[0022]FIG. 10 illustrates a transceiver 1000, which is anotherconfiguration of the transceiver 400.

[0023]FIG. 11 illustrates a transceiver 1100, which is anotherconfiguration of the transceiver 400.

[0024]FIG. 12 illustrates a transceiver 1200, which is anotherconfiguration of the transceiver 400.

[0025]FIG. 13 illustrates a communications system with a backplaneinterface.

[0026]FIG. 14 illustrates a transceiver 1400 with automatic polarityswap according to embodiments of the present invention.

[0027]FIG. 15 illustrates a flowchart that further describes automaticpolarity swap according to embodiments of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0028]FIG. 1 illustrates a multi-port transceiver 100 according toembodiments of the present invention. Transceiver 100 includes aplurality of serial ports 104 a-d, a plurality of parallel ports 102a-b, and a bus 106. Each of the plurality of serial ports 104 is capableof transmitting and receiving data in a serial format, and each of theparallel ports 102 is capable of transmitting and receiving data in aparallel format. For example, the serial ports 104 could be transmittingand receiving serial data with corresponding switches (e.g. MACs) 108a-d.

[0029] The transceiver 100 also includes a bus 106 that is coupled tothe serial ports 104 a-d and the parallel ports 102 a and 102 b. The bus106 enables any serial port 104 to be connected to any other serial port104 and to any parallel port 102 for data transmission, and vice versa.Therefore, data can be transmitted from any switch 108 to any otherswitch 108, or can be transmitted and received to and from the parallelports 102. For example, data received at the serial port 104 a fromswitch 108 a can be routed to the serial port 104 c by the bus 106, fortransmission to the switch 108 c. Additionally, data from the switch 108a can be routed to the other serial ports 104 b-d and to the parallelports 102 a and 102 b through the bus 106.

[0030]FIG. 2 illustrates that each serial port 104 can include aserial-to-parallel converter 202, so that serial data processed by theport 104 can be converted to parallel data, and vice versa. In otherwords, serial data received by serial ports 104 from correspondingswitches 108 can be converted to parallel data and routed on the bus106. The serial-to-parallel converters 202 are bi-directional, so thatparallel data from the bus 106 can be converted to serial data fortransmission from the serial port 104 to the corresponding switch 108.Furthermore, the parallel data from the bus 106 can also be converted toserial for transmission to the switch 108.

[0031]FIG. 2 also illustrates the bus 106 to have a “ring structure”that enables the data to be sent from one adjacent port 104 to anotheradjacent port 104. For example, data from port 104 a is directlytransmitted to ports 104 b and 104 c over the ring structure of the bus106. Therefore, data from any one port 104 can be connected to anotherport 104 using the bus 106 by transmitting data around the ringstructure of the bus from one port 104 to another port 104. Furthermore,the bus 106 transmits data in a parallel format since it is connected tothe parallel side of the serial to parallel converters 202. The parallelformat of the bus 106 enables parallel data to be tapped out from thebus 106 at the parallel ports 102 a and 102 b. The ring structure of thebus 106 will be further described herein.

[0032]FIG. 3 illustrates a flowchart 300 that further describes theoperation of the transceiver 100 in the routing of serial data betweenports. In step 302, serial data is received at a first serial port 104,from a switch 108 for example. In step 304, the serial data is convertedto parallel data. In step 306, the parallel data is routed from oneadjacent port 104 to another via the bus 106 until a destination port104 is reached. In step 308, the parallel data is converted back toserial. In step 310, the serial data is transmitted from the serialdestination port 104, to a destination switch 108 for example.

[0033] The ports of the transceiver 100 can be configured to operateover a number of different data standards, as will be described furtherherein. For example, the serial ports 104 can transmit data to theswitches 108 according to an XAUI serial protocol. The XAUI serial datais converted to XGMII parallel data for transmission over the parallelbus 106, and therefore the XGMII parallel data can be tapped-out by theparallel ports 102 a and 102 b.

[0034]FIG. 3 illustrates a flowchart 300 that further describes theoperation of the transceiver 100 in the routing of data between serialports. In step 302, serial data is received at a first serial port 104,from a switch 108 for example. In step 304, the serial data is convertedto parallel data. In step 306, the parallel data is routed from oneadjacent port 104 to another port 104 via the bus 106 until adestination port 104 is reached. In step 308, the parallel data isconverted back to serial data. In step 310, the serial data istransmitted from the serial destination port 104, to a destinationswitch 108 for example. In an optional step (not shown), the paralleldata can be tapped, prior to being serialized, and transmitted forfurther processing at another destination.

[0035] Furthermore, the inverse operation can also be performed.Parallel data is received at a parallel port 102 and routed to the otherparallel port 102 or routed to a serial destination port 104. If routedto a serial destination port, then the data is serialized prior totransmission.

[0036]FIG. 4 illustrates a multi-port Serdes transceiver 400, which isone embodiment of the transceiver 100. The Serdes transceiver 400includes multiple parallel ports 102 and serial ports 104, and includesthe flexibility to connect any one of the parallel ports 102 to anotherparallel port 102 or to a serial port 104, or both. Furthermore, themultiport transceiver chip 400 can connect any one of the serial ports104 to another serial port 104 or to one of the parallel ports 102.

[0037] More specifically, the Serdes transceiver chip 400 includes twoparallel transceiver ports 102 a,b, and four serial transceiver ports104 a-d. However, the invention is not limited to the number of portsshown. Other configurations having a different number of ports could beused. The parallel transceiver ports 102 a,b transmit and receive datain a parallel format. The parallel transceiver ports 102 a,b can beXGMII parallel ports, for example, where the XGMII transceiver protocolis known to those skilled in the arts. Each XGMII port 102 can include74 data pins, for example, operating at {fraction (1/10)} the data rateof the serial ports 104. For example, the 74 pins can transmit 36 datasignals and receive 36 data signals, simultaneously, and 2 clock signals(1 transmit and 1 receive).

[0038] The four serial ports 104 a-d can be XAUI serial ports, andtransmit and receive data in a serial format. Each serial port 104 canbe a quad serial port having four serial differential data lines usingthe XAUI protocol that is known to those skilled in the arts. Inembodiments of the invention, the serial ports 104 can operate at datarates of 3.125 GHz, 2.5 GHz, and 1.25 GHz. In other words, thetransceiver chip 100 is a mult-rate device. However, the XAUI data ratesabove are effectively quadrupled since there are four serial data linesin each serial port 104. Therefore, the 2.5 GHz data rate is equalvalentto a 10 GHz data rate. As discussed above, the parallel data rates canoperate at {fraction (1/10)} of the data rates of the serial data.

[0039] The serial ports 104 can be further described as 10 Gigabitextension sub-letter (XGXS). In other words, XGXS defines theparallel-to-serial conversion between the parallel XGMII protocol toserial XAUI protocol, according to the IEEE Std 802.3ae, the entirestandard of which is incorporated herein by reference. The serial ports104 receive serial XAUI data and convert it to parallel XGMII dataaccording the XGXS protocol. The parallel XGMII data is routed fromadjacent port to adjacent port on the parallel bus 106.

[0040] As discussed above, the parallel ports 102 and the serial ports104 are linked together by the parallel bus 106. The parallel bus 106enables data to travel between all the ports 102 and 104. Morespecifically the bus 106 enables data to travel from one parallel port102 to another parallel port 102, and to travel from one parallel port102 to a serial port 104. Multiplexers 402 connect the bus 106 to theparallel ports 102 and to the serial ports 104. The serial port 104performs a parallel to serial conversion when receiving parallel datathat is to be sent out serial. Likewise the bus 106 enables data totravel from one serial port 104 to another serial port 104, and totravel between a serial port 104 and a parallel port 102. The parallelport 102 enables parallel data to be tapped from the parallel bus 106 sothat parallel data (e.g. XGMII data) can be transmitted from thetransceiver 400. The multi-port Serdes transceiver 400 is highlyflexible in being able to connect multiple parallel ports 102 tomultiple serial ports 104, and vice versa.

[0041] In embodiments, the Serdes transceiver chip 400 can beimplemented on a single CMOS substrate. For example, the Serdestransceiver chip 400 can be implemented using a low power 0.13-micronCMOS process technology, which lends itself to higher levels ofintegration and application.

[0042] The transceiver 400 enables dual unit operation, where oneparallel port 102 is paired up with two of the serial ports 104 and theother parallel port 102 is paired up with the other two serial ports104. For example, parallel port 102 a can be paired with serial ports104 a and 104 b. Likewise, the parallel port 102 b can be paired withserial ports 104 c and 104 d. However, there is complete selectivity ofthe ports that are grouped together for dual unit operation. Forexample, parallel port 102 a can be paired with either serial ports 104a and 104 b, or serial ports 104 c and 104 d. In a backplaneconfiguration, this provides flexibility to connect a parallel port toone or more serial ports, and with redundancy.

[0043] The transceiver 400 also includes a packet bit error rate tester(BERT) 406. The packet BERT 406 generates and processes packet test datathat can be transmitted over any of the serial ports 104 to perform biterror testing. Any type of packet data can be generated to perform thetesting and at different data rates. For example, the packet BERT 406can generate packet data that can be used to test the Serdes data link.As such, the packet BERT 406 provides a built-in self test for theSerdes data link. The packet BERT 406 generates test data that is sentover one or more of the serial ports 104 using the bus 106 to performthe bit error rate testing of the Serdes data link. For example, thepacket BERT 406 can generate test data for a data link formed byenabling the serial ports 104 a and 104 b to connect the switch 108 a tothe switch 108 c. Likewise, the packet BERT 406 can capture test datareceived over any one of the serial ports 104 or parallel ports 102using the bus 106 for comparison with test data that was sent out. A biterror rate can then be determined based on this comparison.

[0044] In one embodiment, the packet BERT 406 is RAM-based so that thetest data is stored and compared in a RAM memory to perform the biterror rate test. In another embodiment, the packet BERT 406 is logicbased so that the test data is generated by a logic function, andtransmitted across a Serdes link. Upon receipt back, the test data isre-generated by the logic packet BERT 406, for comparison with theoriginal test data that was sent over the Serdes data link. A RAM packetBERT 406 is more flexible than a logic packet BERT 406 because there isno limitation on the data that can be stored in the RAM packet BERT 406.However, a logic packet BERT 406 is more efficient in terms of substratearea because a RAM occupies more area than a logic circuit.

[0045] Since the packet BERT 406 shares the same bus 106 with the serialports 104, the packet BERT 406 can monitor (or “snoop”) between theserial ports 104. In other words, if data is being transmitted from oneserial port 104 to another serial port 104, the packet BERT 406 cancapture and store a portion of this data for bit error testing. In oneembodiment, the packet BERT 406 “blindly” captures data being sent fromone serial port 104 to another serial port 104. In another embodiment,the packet BERT 406 starts capturing data after a particular byte ofdata is transmitted. In another embodiment, the packet BERT 406 startscapturing data after an error event occurs. The packet BERT 406 isfurther described in U.S. patent application Ser. No. 10/681,244, filedon Oct. 9, 2003, which is incorporated by reference herein in itsentirety.

[0046] The Serdes transceiver chip 400 also includes the ability toinclude other optional logic blocks 408 that are not necessary for theoperation of the Serdes transceiver. In other words, the logic blocks408 could be customer driven logic blocks or some other type of logicblock. These optional logic blocks 408 can transmit and receive dataover the serial ports 104 or parallel ports 102 using the bus 106. Thepacket BERT 406 and the optional blocks 408 connect to the bus 106 usingthe multiplexers 404.

[0047] The Serdes transceiver chip 400 also includes a managementinterface 412 that enables the configuration of the portions (parallelports 102, series port 104, packet BERT 406, and optional logic blocks408) of the transceiver chip 100. The management interface 412 includestwo pads 414 that enable two different management chips to program andcontrol the portions of the transceiver chip 400 using MDIOs blocks 416.For example, one management chip connected to pad 414 a could controlthe parallel port 102 a and the serial ports 104 a and 104 b, andanother management chip connected to pad 414 b could control theparallel port 102 b and the serial ports 104 c and 104 d. The managementinterface 412 is configured to be compatible with both IEEE Std. 802.3clause 45 and the IEEE Std. 802.3 clause 22 management standards. Inother words, one management pad 414 a and MDIO block 416 a can beprogrammed to be responsive to clause 45 electricals and protocol, andthe other management pad 414 b and MDIO block 416 b could be responsiveto clause 22 electricals and protocol. Furthermore, the management pads414 and MDIO blocks can mix and match clause 22 and clause 45 electricaland protocols. For example, management pad 414 a and MDIO block 416 acan be responsive to clause 22 electricals and clause 45 protocols, andvice versa. Similar mix and match can be done for the management pad 414b and the MDIO block 416 b. The management data pads are furtherdescribed in U.S. patent application Ser. No. ______, titled ”Multipurpose and Integrated Pad Ring for Integrated Circuit”, filedherewith, Attorney Docket No. 1875. 4520000, and U.S. patent applicationSer. No. ______, titled ” Programmable Management I/O Pads for anIntegrated Circuit”, filed herewith, Attorney Docket No. 1875. 4530000,both of which are incorporated by reference herein in its entirety.

[0048]FIG. 5 illustrates the substrate layout 500 for the Serdestransceiver 400 according to embodiments of the invention. The substratelayout 500 is configured to minimize the substrate area of thetransceiver 400, and efficiently provide the port interconnectionsdescribed above.

[0049] The substrate layout 500 is configured so that the parallel ports102 a,b and the serial ports 104 a-d are on the outer perimeter of thesubstrate 200, as shown. In other words, the serial ports 104 a and 104b are on a first side of the substrate layout 500 and the serial ports104 c and 104 d are on a second side of the substrate layout 500. Theparallel port 102 a is on a third side of the substrate layout 500. Andthe parallel port 102 b is on a fourth side of the substrate layout 500.A logic core 502 is at the center of the substrate 500, where the logiccore 502 operates the bus 106 and the serial 104 and parallel 102 dataports. The management interface 412, the packet BERT 406, and theoptional logic blocks 408 a-c are adjacent to the logic core 502 asshown. The bus 106 can be described as a “ring” structure (or donut“structure”) around the logic core 502, and is placed in between thelogic core 502 and the data ports 102 and 104 that occupy the parameterof the substrate layout 500. Furthermore, the ring structure of the bus106 also provides efficient communication between the logic core 502 andthe various data ports 102 and 104. Furthermore, the ring structure ofthe bus 106 also provides efficient communication between the managementinterface 412, the packet BERT 406, the optional logic blocks 408, andthe various data ports 102 and 104.

[0050] The bus 106 is illustrated as 8 sections 106 a-106 g for ease ofillustration. Each section provides an interface to the respective dataports 102 or 104 that are adjacent to the respective sections.

[0051]FIG. 6 represents one of the 8 sections 106 a-106 g of the bus 106according to embodiments of the present invention. Each section of thebus 106 can be represented as two paths 608 and 610. Data enters the bus106 through a buffer 602 and proceeds to its destination along the path608 and through the buffers 604. Data passes from one section to anothersection of the bus 106 using the path 610 and passing through thebuffers 612. The mux 606 represents data passing from the bus 106 to afunctional block, such as a data port 102, 104 or the packet BERT 406.The actual wires and buffers on the bus 106 are matched to minimizesignal distortion.

[0052] In embodiments, the data wires in the bus 106 are deposited onthe substrate 500 in a particular fashion. Namely, a power or ground isplaced between adjacent (or near by) data wires. Furthermore, adjacentdata wires on the bus 106 are placed on two separate layers. Therefore,a power or ground will be above or below a data wire, and adjacent to adata wire. Therefore, two nearby data wires will not be located directlyadjacent one another, but instead will be positioned diagonal to eachother, thereby reducing cross talk.

[0053] The parallel bus 106 is further described in U.S. patentapplication Ser. No. ______, titled “Cross Link Multiplexer Bus”,Attorney Docket No. 1875.3640002, filed herewith, and incorporated byreference herein in its entirety.

[0054] The multi-port Serdes transceiver 400 supports multiple differentdata protocols at the pads including XGMII, TBI, RTBI, HSTL, SSTL, orLVTTL protocols, and others.

[0055]FIG. 7 further illustrates an example layout of the bus 106. Thewires 702 between data ports 102, 104 are configured to have the samepath lengths so as to minimize signal distortion. In other words, wires702 a-d are deposited so as to have the same path length so as to reducesignal distortion.

[0056] The multi-port Serdes transceiver 400 includes the ability tochange the timing of the data ports 102 and 104. This includes theability to change the timing between the data and clock signals. Inother words, the registers in the data ports 102 and 104 can bere-programmed to operate at different timing protocols.

[0057] The Serdes transceiver 400 is highly flexible and can beconfigured to provide multiple different transceivers by enabling anddisabling various serial and parallel data ports. This is accomplishedusing a configuration logic circuit 418 that controls the registers andtiming of the data ports 102 and 104, and also enables/disables thesedata ports. As a result, several different transceiver products can beconfigured from a single semiconductor die that is manufactured with the4 serial data ports and 2 parallel data ports. For instance, FIG. 1illustrates an embodiment, where all four serial ports 104 and bothparallel ports 102 are enabled and accessible to exchange data. Thetransceiver 400 represents the maximum capability that can be achievedfrom the 4 serial and two parallel data ports. Other specific examplesare discussed below, but the invention is not limited to these examples.

[0058]FIG. 8 illustrates a transceiver 800 having 4 serial XGXS dataports 104. The two parallel ports 102 have been disabled usingconfiguration logic 418 and/or by not bonding the parallel ports to theoutput pins of the semiconductor package. The transceiver 800 enablesany of the switches 108 to exchange data with any of the other switches108.

[0059]FIG. 9 illustrates a transceiver 900 having 2 serial XGXS dataports 104 a and 104 b and two XGMII parallel data ports 102 a and 102 b.The other two serial data ports 104 c and 104 d have been disabled usingconfiguration logic 418 and/or by not bonding the ports to the outputpins of the semiconductor package. The transceiver 900 enables theswitch 108 a to exchange data with the switch 108 b, and allows theparallel XGMII data to be tapped from the parallel bus 106 using theparallel XGMII data ports 102 a 102 b.

[0060] In another embodiment of FIG. 9, the timing of the serial andparallel ports is varied to provide another transceiver product. Forinstance, the two XGXS serial ports can be configured as 8 Serdes portsthat operate at a slower data rate than the XGXS data ports. Likewise,the two XGMII parallel data ports can be configured as 8 TBI data portsthat also operate at a slower data rate. In general, the timing of thedata ports can be revised and reconfigured for each of the transceiverconfigurations shown herein.

[0061]FIG. 10 illustrates a transceiver 1000 having 2 serial XGXS dataports 104 a and 104 b and only one XGMII parallel data port 102 a. Theother two serial data ports 104 c and 104 d and the parallel port 102 bhave been disabled using configuration logic 418 and/or by not bondingthe ports to the output pins of the semiconductor package. Thetransceiver 1000 enables the switch 108 a to exchange data with theswitch 108 b, and allows the parallel XGMII data to be tapped from theparallel bus 106 using the parallel XGMII data port 102 a.

[0062]FIG. 11 illustrates a transceiver 1100 having 2 serial XGXS dataports 104 a and 104 c and no XGMII parallel data port 102 a. The othertwo serial data ports 104 c and 104 d and the parallel ports 102 havebeen disabled using configuration logic 418 and/or by not bonding thedisabled ports to the output pins of the semiconductor package. Thetransceiver 1100 enables the switch 108 a to exchange data with theswitch 108 c.

[0063]FIG. 12 illustrates a transceiver 1200 having 3 serial XGXS dataports 104 a, 104 b, and 104 d and one XGMII parallel data port 102 a.The other serial data ports 104 c and the parallel port 102 a have beendisabled using configuration logic 418 and/or by not bonding thedisabled ports to the output pins of the semiconductor package. Thetransceiver 1200 enables the switches 108 a, 108 b, and 108 d toexchange data with each other.

[0064] Based on the above discussion, it is apparent that the basetransceiver 400 is highly flexible and enables multiple transceiverproducts, with different capabilities and price points, to be configuredand sold from the base semiconductor die.

Automatic Polarity Swap

[0065]FIG. 13 illustrates a communications system 1300 having a firstSerdes transceiver 100 a that communicates data with a second Serdestransceiver 100 b through an interface 1303, that may be a backplane forexample. The Serdes transceivers 100 a and 100 b can be any type of thetransceivers discussed herein, or any other type of transceiver. TheSerdes transceiver 100 a can be represented as having a differentialinput 1301 p and 1301 n and a differential output 1302 p and 1302 n.Likewise, the Serdes transceiver 100 b can be described as having adifferential input 1304 p and 1304 n, and a differential output 1306 pand 1306 n.

[0066] During the configuration of the backplane 1303, the differentialoutput 1302 of the transceiver 100 a can be mistakenly cross-connectedwith the differential input 1304 of the Serdes transceiver 100 b. Inother words, the 1302 n output of the transceiver 100 a can bemistakenly connected to the 1304 p input of the transceiver 100 b.Likewise, the 1302 p output of the transceiver 100 a can be mistakenconnected to the 1304 n input of the transceiver 100 a. The result ofsuch a cross-connection is that invalid data words are received at theSerdes transceiver 100 b, which causes an increase in the bit error rate(BER).

[0067]FIG. 14 illustrates an apparatus and method of automatic polarityswap to address the cross-connection problem discussed with reference toFIG. 13. FIG. 14 illustrates a transceiver 1400 having an error checkand correction module 1401. The error check and correction module 1401includes an error check 1402 and a exclusive OR (X-OR) 1404. The errorcheck and correction module 1401 is coupled to the output of theserial-to-parallel converter 202 and checks the digital output of theserial-to-parallel converter 202 to determine if it is a valid digitalword. If it is not a valid digital word, then the module 1401 performsan automatic polarity flip of the digital word.

[0068] The error check and correction module 1401 includes an errorcheck 1402 at the output of the parallel-to-serial converter 202 a. Theerror check module 1402 examines the digital word at the output of theparallel-to-serial converter 1402 and determines if it is a validdigital word within the context of the communications system 1300. Forexample, the error check module 1402 can include a RAM memory thatstores the possible digital word combinations for comparison with thedigital word output of the serial-to-parallel converter 202. If thedigital word output of the serial-to-parallel converter 202 a does notmatch any one of the possible combinations, then the digital word outputof the serial-to-parallel converter is not a valid digital word.Accordingly, one possibility is that the interface 1303 iscross-connected as discussed above. If this is so, then flipping thepolarity of the bits that make up the digital word, will convert theinvalid digital word to a valid digital word. This can be accomplishedusing an exclusive-OR gate 1404. When the error check module 1402detects an invalid digital word, then the error check module 1402 sendsa control bit logic “1” to the exclusive-OR 1404, which causes theexclusive OR to invert the digital output from the serial-to-parallelconverter, and generate a inverted digital word 1405. If the error wasintroduced by the cross-connection, then the inverted digital word 1405will be a valid digital word.

[0069] The error check module 1402 outputs a control bit “0” when itdetermines that the digital word at the output of the serial-to-parallelconverter is a valid digital word. A control bit “0” does not invert thedigital word, so that the digital word passes unchanged for furtherprocessing.

[0070] The error check and correction module 1401 can be implementedusing other configurations as will be understood by those skilled in thearts based on the discussion given herein. For instance, a logic circuitother than an X-OR can be used to flip the polarity of the digital wordif it is invalid.

[0071] An advantage of implementing the automatic polarity swap is thatcross-connect errors are rectified quickly and easily, without having tore-wire or re-configure any hardware. Furthermore, the polarity swap canbe implemented on the transmit side or the receive side. However, thereceive implementation is shown in FIG. 14. The transmit implementationwill be apparent based the description related to FIG. 14.

[0072]FIG. 15 illustrates a flowchart 1500 that further describes anautomatic polarity swap according to embodiments of the presentinvention.

[0073] In step 1502, a serial differential signal is received. In step1504, the serial differential signal is converted to a paralleldifferential data word.

[0074] In step 1506, the parallel differential data word is examined todetermined if it is a valid data word for the correspondingcommunications system. For instance, the parallel differential data wordcan be compared with valid data words that are stored in a RAM. If theparallel differential data word is valid, then it is passed unmodifiedfor further processing. For example, a valid data word can bere-serialized and transmitted to a destination switch or MAC.

[0075] In step 1508, the parallel differential data word is inverted ifthe parallel differential data word is found to be invalid in step 1506.For instance, a logic circuit (such as the X-OR 1404) can be used toinvert the parallel data word is if it is invalid.

[0076] In step 1510, the inverted parallel data word can be re-examinedto determine if it is now a valid data word, and if so the invertedparallel data word can be further processed. For example, the invertedparallel data word can be serialized and retransmitted to a destinationswitch, or MAC.

Conclusion

[0077] Example embodiments of the methods, systems, and components ofthe present invention have been described herein. As noted elsewhere,these example embodiments have been described for illustrative purposesonly, and are not limiting. Other embodiments are possible and arecovered by the invention. Such other embodiments will be apparent topersons skilled in the relevant art(s) based on the teachings containedherein. Thus, the breadth and scope of the present invention should notbe limited by any of the above-described exemplary embodiments, butshould be defined only in accordance with the following claims and theirequivalents.

What is claimed is:
 1. A transceiver, comprising: multiple parallelports; multiple serial ports; and a bus connecting said multipleparallel ports and said multiple serial ports on a common substrate withsaid multiple parallel ports and said multiple serial ports.
 2. Thetransceiver of claim 1, wherein said bus is configured to have a ringshape.
 3. The transceiver of claim 1, wherein said bus is configured tohave a ring shape around a logic core.
 4. The transceiver of clam 1,further comprising a packet bit error rate tester (BERT) connected tosaid bus, said packet BERT able to determine bit error rates of at leastone of said multiple parallel ports and said multiple serial ports. 5.The transceiver of claim 1, wherein said multiple parallel ports includetwo parallel ports and said multiple serial ports includes four serialports.
 6. The transceiver of claim 1, wherein said multiple parallelports are XGMII parallel ports.
 7. The transceiver of claim 1, whereinsaid multiple serial ports are XAUI serial ports.
 8. The transceiver ofclaim 1, wherein said serial ports convert between a XAUI serialprotocol and a XGMII parallel protocol using a XGXS conversion protocol.9. The transceiver of claim 1 wherein said bus is a parallel bus. 10.The transceiver of claim 9, wherein said parallel bus includes multipletransmission lines having a common path length.
 11. The transceiver ofclaim 9, wherein each of said serial ports include a serial-to-parallelconverter, a parallel port of said serial-to-parallel converterconnected to said parallel bus.
 12. The transceiver of claim 1, furthercomprising at least one management pad, said management pad able todetermine data protocols and electricals for said transceiver.
 13. Thetransceiver of claim 12, wherein said management pad is responsive totwo or more protocols.
 14. The transceiver of claim 13, wherein said twoor more protocols include an IEEE Std 802.3 clause 22 managementstandard and an IEEE Std 802.3 clause 45 management standard.
 15. Thetransceiver of claim 12, wherein said management pad is responsive to adata protocol of a first type of standard, and an electrical protocol ofa second type of standard.
 16. The transceiver of claim 15, wherein saidfirst type of standard is one of an IEEE Std 802.3 clause 45 standardand an IEEE Std 802.3 clause 22 standard, and said second type ofstandard is the other of said IEEE Std 802.3 clause 45 standard and saidEEEE Std 802.3 clause 22 standard.
 17. The transceiver of claim 1,wherein data clock rates of said serial data ports and said paralleldata ports are programmable.
 18. The transceiver of claim 1, whereinsaid multiple serial data ports and said multiple parallel data portscan be enabled and disabled to provide a specific configuration for saidtransceiver.
 19. The transceiver of claim 18, wherein two of saidmultiple serial data ports are enabled.
 20. The transceiver of claim 19,wherein at least one of said multiple serial ports is disabled.
 21. Thetransceiver of claim 18, wherein at least one of said multiple parallelports is enabled.
 22. The transceiver of claim 21, wherein at least oneof said multiple parallel ports is disabled.
 23. The transceiver ofclaim 1, further comprising at least one custom logic block connected tosaid bus.
 24. The transceiver of claim 18, further comprising aconfiguration block that enables and disables said multiple parallelports and said multiple serial ports to configure said transceiver. 25.The transceiver of claim 24, wherein said configuration block alsodetermines defaults of said transceiver.